As described in the background section of the above-referenced '787 patent application, electrical power for integrated circuits is typically supplied by one or more direct current (DC) power sources. In a number of applications the circuit may require plural regulated voltages that are different from the available supply voltage, which may be relatively low e.g., on the order of three volts or less, particularly where low current consumption is desirable, such as in portable, battery-powered devices. (This architecture may achieve a much high voltage difference in portable applications, for example an input voltage on the order of 4.5-25V and an output voltage Vo on the order of 0.5V-3.7V.) Moreover, in many applications the load current may vary over several orders of magnitude. To address these requirements it has been common practice to employ ripple generator-based converters, such as a hysteresis or ‘bang-bang’ converter of the type shown in FIG. 1.
Such a ripple regulator-based DC—DC voltage converter employs a relatively simple control mechanism and provides a fast response to a load transient. The switching frequency of the ripple voltage regulator is asynchronous, which is advantageous in applications where direct control of the switching frequency or the switching edges is desired. For this purpose, the ripple voltage regulator of FIG. 1 employs a hysteresis comparator 10, that switchably controls a gate drive circuit 20, respective output drive ports 22 and 23 of which are coupled to the control or gate drive inputs of a pair of electronic power switching devices, respectively shown as an upper P-MOSFET (or PFET) device 30 and a lower N-MOSFET (or NFET) device 40. These FET switching devices have their drain-source paths coupled in series between first and second reference voltages (Vdd and ground (GND)).
The gate drive circuit 20 controllably switches or turns the two switching devices 30 and 40 on and off, in accordance with a pulse width modulation (PWM) switching waveform (such as that shown at PWM in the timing diagram of FIG. 2) supplied by comparator 10. The upper PFET device 30 is turned on and off by an upper gate switching signal UG applied by the gate driver 20 to the gate of the PFET device 20, and the lower NFET device 30 is turned on and off by a lower gate switching signal LG applied by the gate driver 20 to the gate of the NFET device 30.
A common or phase voltage node 35 between the two power FETs 30/40 is coupled through an inductor 50 to a capacitor 60, which is referenced to a prescribed potential (e.g., ground (GND)). The connection 55 between the inductor 50 and the capacitor 60 serves as an output node, from which an output voltage Vout (shown as triangular waveform Output in FIG. 2) is derived. In order to regulate the output voltage relative to a prescribed reference voltage, the output node 55 is coupled to a first, inverting (−) input 11 of the hysteresis comparator 10, a second, non-inverting (+) input 12 of which is coupled to receive a DC Reference voltage.
In such a hysteretic regulator, the output PWM signal waveform produced by hysteresis comparator 10 transitions to a first state (e.g., goes high) when the output voltage Vout at node 55 falls below the reference voltage Reference (minus the comparator's inherent hysteresis voltage Δ). Conversely, the comparator's PWM output transitions to a second state (e.g., goes low) when the output voltage Vout exceeds the reference voltage plus the hysteresis voltage Δ. The application of or increase in load will cause the output voltage (Vout) to decrease below the reference voltage, in response to which comparator 10 triggers the gate drive to turn on the upper switching device 30. Because the converter is asynchronous, the gate drive control signal does not wait for a synchronizing clock, as is common in most fixed frequency PWM control schemes.
Principal concerns with this type of ripple voltage regulator include large ripple voltage, DC voltage accuracy, and switching frequency. Since the hysteretic comparator 10 directly sets the magnitude of the ripple voltage Vout, employing a smaller hysteresis Δ will reduce the power conversion efficiency, as switching frequency increases with smaller hysteresis. In order to control the DC output voltage, which is a function of the ripple wave shape, the peak 71 and the valley 72 of the output ripple voltage (Output, shown in FIG. 2) is regulated. For the triangular wave shape shown, the DC value of the output voltage is a function of the PWM duty factor. The output voltage wave shape also changes at light loads, when current through the inductor 50 becomes discontinuous, producing relatively short ‘spikes’ between which are relatively long periods of low voltage, as shown by the DISCON waveshape in FIG. 2. Since the ripple voltage wave shape varies with input line and load conditions, maintaining tight DC regulation is difficult.
In addition, improvements in capacitor technology will change the ripple wave shape. In particular, the current state of ceramic capacitor technology has enabled the equivalent series resistance or ESR (which produces the piecewise linear or triangular wave shape of the output voltage waveform shown in FIG. 2) of ceramic capacitors to be reduced to very low values. At very low values of ESR, however, the output voltage's ripple shape changes from triangular to a non-linear shape (e.g., parabolic and sinusoidal). This causes the output voltage to overshoot the hysteretic threshold, and results in higher peak-to-peak ripple. As a result, the very improvements that were intended to lower the output voltage ripple in DC—DC converters can actually cause increased ripple when used in a ripple voltage regulator.
In accordance with the invention disclosed in the '787 application, shortcomings of conventional ripple voltage regulators, including those described above, are effectively obviated by the synthetic ripple voltage regulator shown in FIG. 3. This synthetic ripple voltage regulator generates an auxiliary voltage waveform, that effectively replicates or mirrors the waveform ripple current through the output inductor 50, and uses this auxiliary voltage waveform to control toggling of the hysteretic comparator 10. Using such a reconstructed current for the purpose of ripple voltage regulation results in low output ripple and simplified compensation.
More particularly, the synthetic ripple voltage regulator of FIG. 3 employs a transconductance amplifier 110, the output of which is coupled to a ‘ripple voltage’ capacitor 120. The transconductance amplifier 110 produces an output current IRAMP proportional to the voltage across inductor 50, which is interconnected between a node 35 common with the upper and lower MOSFETs (respective gate drives 21 and 22 for which are produced by a gate drive circuit 20), and an output node 55. The ripple voltage capacitor 120 transforms this output current ramp into an inductor current-representative voltage having the desired waveform shape. A benefit of synthesizing the ripple waveform based on inductor current is the inherent feed-forward characteristic. For a step input voltage change, the current IRAMP produced by the transconductance amplifier 110 will change proportionally to modify the conduction interval of the power switching devices.
For this purpose, transconductance amplifier 110 has a first, non-inverting (+) input 111 coupled to the phase node 35 and a second, inverting (−) input 112 coupled to output voltage node 55 at the other end of inductor 50, so that the transconductance amplifier 110 effectively ‘sees’ the voltage across inductor 50. The output voltage node 55 is further coupled to a first terminal 121 of capacitor 120 and to the inverting (−) input 141 of an error amplifier 130 inserted upstream of the hysteresis comparator 10. Error amplifier 130 serves to increase the DC regulation accuracy, providing high DC gain to reduce errors due to ripple wave shape, various offsets, and other errors. Error amplifier 130 has a second, non-inverting (+) input 132 thereof coupled to receive the voltage Reference, while its output 133 is coupled to the non-inverting (+) input 12 of hysteresis comparator 10. In the configuration of FIG. 3, the output of the error amplifier 130 follows the load current. The transconductance amplifier 110 has its output 113 coupled to a second terminal 122 of the capacitor 120 and to inverting (−) input 11 of the hysteresis comparator 10.
The operation of the synthetic ripple voltage regulator of FIG. 3 may be understood with reference to the set of waveform timing diagrams of FIG. 4. As a non-limiting example, the regulator voltage may be set at a value of Reference=1 VDC and the hysteresis comparator 10 may trip with +/−100 mV of hysteresis. The inductance of inductor 50 is 1 μH and the output capacitance is 10 μF. The line M1 (at the 30 μsec time mark) in FIG. 4 represents a change in input voltage from a value on the order of 3.6 VDC prior to M1 to a value on the order of 4.2 VDC at M1 and thereafter.
The upper waveform 501 corresponds to the ripple voltage generated across the ripple voltage capacitor 120; the middle waveform 502 is the current through inductor 50, and the lower waveform 503 is the output voltage at node 55. The similarity of the respective ripple and inductor current waveforms 501 and 502 is readily apparent, as shown by respective step transitions 511/521 and 512/522 therein, at t=20 μs and t=50 μs. As shown by waveform 502, the converter is initially supplying an inductor current on the order 100 mA for an input supply voltage of 3.6 VDC. This inductor current is discontinuous and the switching frequency has a relatively stable value on the order of 900 kHz.
At the transient 521 (t=20 μs) in waveform 502, there is a stepwise (×10) increase in the load current from 100 mA to a value on the order of 1 A, and the switching frequency increases to a frequency on the order of 1.5 MHz. From the output voltage waveform 503, it can be seen that the amount of ripple 531 occurring at this transient is relatively small (on the order of only +/−3 mV, which is well below that (+/−100 mV) of the prior art regulator of FIG. 1, during discontinuous operation, where load current=100 mA, and then drops to +/−1.5 mV).
At the M1 or t=30 μs time mark, there is a stepwise increase in input voltage from 3.6 VDC to 4.2 VDC, and the switching frequency increases to almost 2.3 MHz, yet the levels of each of waveforms 501, 502 and 503 remain stable. Subsequently, at t=50 μs, there is a step transient 512 in the inductor/load current waveform 501, which drops back down from 1 A to 100 mA, and the switching frequency settles to a value on the order of 1.3 MHz. As can be seen in the output voltage waveform 503, like the ripple 531 occurring at the t=20 μs transient, the amount of ripple 532 for this further transient is also relatively small (on the order of only +−3 mV and dropping to +/−1.5 mV), so that the output voltage may be effectively regulated at a value on the order of the voltage Reference of 1 VDC.